Field of the Invention
The invention relates to a memory element having the following characteristics:
(a) the emitters of first and second transistors of a first transistor pair are coupled and are connected through a current source to a terminal for a first supply potential;
(b) the collector of the first transistor of the first transistor pair is connected to the coupled emitters of first and second transistors of a second transistor pair;
(c) the collector of the second transistor of the first transistor pair is connected to the coupled emitters of first and second transistors of a third transistor pair;
(d) the collectors of the transistors of the second and third transistor pairs are coupled in pairs and each connected to a first terminal of a respective resistor;
(e) a second terminal of each resistor is connected through the collector-to-emitter path of one respective transistor of a fourth transistor pair to a second supply potential;
(f) the transistors of the fourth transistor pair are connected as an emitter follower circuit with respect to the second supply potential;
(g) the collector of at least one of the transistors of the fourth transistor pair is connected to an output signal terminal and through a resistor to the terminal for the second supply potential;
(h) the base of the first transistor of the third transistor pair is connected to the collector of the second transistor of the third transistor pair;
(i) the base terminals of the first transistors of the first and second transistor pairs are each terminals for a respective input signal; and
(j) the base terminals of the second transistors of the first, second and third transistor pairs are each terminals for a respective reference signal.
Such memory elements are preferably used in digital circuits that operate at a high clock frequency. The maximum possible operating speed of the memory element is determined substantially by the capacitive load that is applied to the paired coupled collectors of the transistors of the second and third transistor pairs. Such capacitances are composed primarily of the capacitance between the metallizing and the substrate of connecting lines, with which the components connected to a circuit node are connected, and the capacitance between the collectors and the substrate of the connecting transistors.
Heretofore, one transistor each has been used for setting and for resetting the memory element, and its collector-to-emitter path has been connected between the base terminal of one of the transistors of the third transistor pair and the coupled emitter terminals of those transistors. Since the base terminal of each transistor of the third transistor pair is connected crosswise to the collector terminal of the respectively other transistor, the capacitive load at the collectors of the transistors of the third transistor pair becomes even higher through one additional transistor for setting or resetting the memory element. Therefore, the maximum attainable operating speed is reduced.